ANTI-TAMPER DIGITAL CLOCKS OPTIONS

Anti-Tamper Digital Clocks Options

Anti-Tamper Digital Clocks Options

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a 2nd circuit that gives a next monotone sign in the course of a next clock Examine time period connected with the clock, whereby the next clock Appraise period of time covers a unique time than the main clock Examine time frame;

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an Appraise circuit, activated from the clock, that takes advantage of the 1st plurality of delayed monotone signals or the second plurality of delayed monotone signals to detect a clock fault.

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SUMMARY An facet of the current creation could reside in a method for detecting clock tampering. In the strategy a plurality of resettable hold off line segments are supplied. Resettable delay line segments between a resettable delay line segment affiliated with a minimum amount delay time as well as a resettable delay line section associated with a greatest hold off time are each related to discretely escalating delay situations.

Resettable hold off line segments in between a resettable delay line section related to a least hold off time as well as a resettable hold off line segment linked to a optimum delay time are Every affiliated with discretely escalating delay instances. An Appraise circuit is induced by a clock and takes advantage of the plurality of delayed monotone signals to detect a voltage fault.

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An additional element of the invention may perhaps reside in an apparatus for detecting clock tampering, comprising: initial circuit, a primary plurality of resettable hold off line segments, a second circuit, a 2nd plurality of resettable hold off line segments, and an Consider circuit. The initial circuit offers a first monotone signal all through a first clock Consider time frame affiliated with a clock. The initial plurality of resettable hold off line segments Every hold off the primary monotone sign to generate a respective to start with plurality of delayed monotone alerts. Resettable hold off line segments in between a resettable delay line segment linked to a least delay time along with a resettable delay line segment linked to a most delay time are Each and every affiliated with discretely escalating delay moments.

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One more facet of the invention may possibly reside in an equipment for detecting voltage tampering, comprising: usually means read more for providing a monotone sign during an evaluate time; indicates for delaying the monotone sign employing a plurality of resettable delay line segments to make a respective plurality of delayed monotone indicators possessing discretely escalating delay occasions between a minimum hold off time plus a highest hold off time; and suggests for using the clock to cause an Assess circuit that uses the plurality of delayed monotone alerts to detect a voltage fault.

An additional element of the invention may possibly reside in an equipment for detecting clock tampering, comprising: signifies for offering a monotone sign through a clock Consider time frame affiliated with a clock; suggests for delaying the monotone sign utilizing a plurality of resettable hold off line segments to produce a respective plurality of delayed monotone signals having discretely raising hold off instances between a least hold off time along with a most delay time; and signifies for utilizing the clock to trigger an Consider circuit that uses the plurality of delayed monotone signals to detect a clock fault.

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